1. Field of the Invention
The present invention aims at novel diac structures especially enabling easing the assembly of such components.
2. Discussion of the Related Art
A conventional diac structure is shown in FIG. 1. The structure is formed from a substrate 1 of a first conductivity type, here type P. On either side of the substrate are formed heavily-doped regions of the opposite type, here, type N, respectively 2 and 3. To obtain a sufficiently high breakdown voltage, the so-called mesa technology is used, which consists of etching grooves at the border between two diacs formed in a same wafer. The angle formed by the groove at the location where it cuts the junction between the P and N+ regions is an important parameter for determining the breakdown voltage at the component periphery. Another important parameter is the choice of the passivation product 4 formed in the grooves.
The upper and lower surfaces of the diac are covered with metallizations M1 and M2. Conventionally, a diac is a device of small size, its thickness being smaller than 0.3 mm and its surface being on the order of 0.5 mm×0.5 mm.
Special packages are thus provided for the diacs, for example, piston systems arranged on either side of a glass tube in which the chip is enclosed.
To avoid difficulties associated with the mesa technology and with the digging of grooves, it has been attempted to make diacs of planar type, for example, such as that shown in FIG. 2, also formed from a P-type substrate 1. The upper and lower surfaces of the substrate are coated with a masking layer, for example, silicon oxide, respectively 11 and 12, provided with a central opening through which is formed an N+-type diffused region, respectively 13 and 14. These planar structures enable obtaining satisfactory planar structures of the junction peripheries, but pose assembly problems. Indeed, it becomes difficult to weld the chip on a metal support wafer since, in case the welding extends laterally beyond its location, a short-circuit is created between one of the N+ regions and the P substrate. Metallizations must thus be provided, for example formed of silver balls 15 and 16, located on N+ regions 13 and 14, which complicates the assembly and increases its cost.
Thus, to assemble a diac of planar type such as that of FIG. 2, very specific packages and assembly modes must be provided.
FIG. 3 illustrates the typical characteristic of a diac. Such a component cannot be assimilated to two head-to-tail zener diodes. Indeed, the existence, when one of the junctions is in avalanche, of another forward junction which injects into the substrate, causes a breakover type effect. Thus, the diac breaks down when the voltage thereacross reaches a value VBO. The voltage then drops to an intermediary voltage Vf as long as the current is in a given range of values. The voltage across the diac rises back if the current comes out of this range. In the example shown in FIG. 3, the value of voltage VBO is 32 volts, the value of voltage Vf is 13 volts, the current at the breakover time is on the order of 0.3 μA (that is, the diac has very slight leaks), and the current corresponding to voltage Vf is in a range on the order of from 10 to 100 milliamperes.
A diac, such as those shown in FIGS. 1 and 2, has a symmetrical characteristic, as shown in FIG. 3. The value of voltage VBO essentially depends on the doping levels of the junctions between the N+ regions and the P substrate. The value of forward voltage Vf essentially depends on the doping level and on the thickness of substrate 1, which can be considered as the floating base of a transistor having its emitter and collector corresponding to the N+ regions. This base must be such that the carriers injected by the forward junction can cross it. The carrier lifetime must thus be long in the base if its width is large, that is, it must be lightly doped. If the base dimension becomes small, the carrier lifetime in this base must be reduced, for example by a metallic diffusion. These various compromises determine above-mentioned voltage Vf.
Generally, semiconductor manufacturers are asked to provide diacs having well established values of VBO and Vf. For example, a diac having a voltage VBO of 32 V±12%, with a voltage drop from VBO to Vf of a minimum 10 V, and with an asymmetry smaller than a few percents of the considered values, will be desired.